IBIS Macromodel Task Group Meeting date: 10 September 2013 Members (asterisk for those attending): Agilent: Fangyi Rao * Radek Biernacki Altera: * David Banas Julia Liu Hazlina Ramly Andrew Joy Consulting: Andy Joy ANSYS: Samuel Mertens * Dan Dvorscak * Curtis Clark Steve Pytel Luis Armenta Arrow Electronics: Ian Dodd Cadence Design Systems: Terry Jernberg * Ambrish Varma Feras Al-Hawari Brad Brim Kumar Keshavan Ken Willis Cavium Networks: Johann Nittmann Celsionix: Kellee Crisafulli Cisco Systems: Ashwin Vasudevan Syed Huq Ericsson: Anders Ekholm IBM: Greg Edlund Intel: Michael Mirmak Maxim Integrated Products: Mahbubul Bari Hassan Rafat Ron Olisar Mentor Graphics: * John Angulo Zhen Mu * Arpad Muranyi Vladimir Dmitriev-Zdorov Micron Technology: * Randy Wolff * Justin Butterfield NetLogic Microsystems: Ryan Couts Nokia-Siemens Networks: Eckhard Lenski QLogic Corp. James Zhou SiSoft: * Walter Katz * Todd Westerhoff Doug Burns * Mike LaBonte Snowbush IP: Marcus Van Ierssel ST Micro: Syed Sadeghi Teraspeed Consulting Group: * Scott McMorrow * Bob Ross TI: Casey Morrison Alfred Chong Vitesse Semiconductor: Eric Sweetman Xilinx: Mustansir Fanaswalla Ray Anderson The meeting was led by Arpad Muranyi ------------------------------------------------------------------------ Opens: - Bob said Scott would like to give a presentation -------------------------- Call for patent disclosure: - None ------------- Review of ARs: - No ARs recorded, but Bob and Arpad worked on adding BIRD 160 language to BIRD 155 ------------- New Discussion: BIRD 155: Arpad showed BIRD 155.1 draft 7. Radek described the changes made from draft 6. Arpad wondered if an "or" should be "and". We decided to keep "or". Bob suggested that a "For example" sentence should be in a separate paragraph from the Other Notes section for Resolve_Exists. Arpad asked about an email comment from Bob, regarding Resolve_Exists. Radek said it would be easier to check just one parameter. We agreed there was no issue. Radek motioned to submit the draft to the open forum. Arpad seconded the motion. No one objected. AR: Arpad submit BIRD 155.1 draft 7 to open forum Walter motioned to recommend rejection of BIRD 150 to the open forum. Arpad seconded. No one objected. Interconnect update: Arpad said that in the last interconnect meeting the BIRD 125 implementation of Walter's case 5 example was discussed. The general feeling was that the BIRD 125 implementation was cumbersome as compared with the EMD proposal. There was no formal decision made about what direction should be taken for the IBIS specification. Arpad showed Scott's DDR Jitter vs. Aggressors Study presentation: Scott narrated the slides. Slide 2: For 25Gbps SerDes, the impact of crosstalk on jitter is significant. Slide 3: In most package designs above 10G, crosstalk is not a local phenomenon, like a tuning fork exciting other tuning forks. This looks random but is quite deterministic. Scott described an experiment performed with an s176p DDR system model. Walter asked if redistribution was included. Scott said it was and clarified that "pad" means the buffer terminal. David said "pad" means different things in bullets 2 and 4. Scott said bullet 2 refers to the package pin pad. Slide 4: The nearest aggressors have the biggest hit, but even with 6 aggressors we have not reached an asymptote. Given a package model, there is no way to know if all significant crosstalk is covered. Signals are often edge aligned so they add up. Walter noted that DQ is broken into 4 bit nibbles so there may not be too much alignment. He asked if Scott would recommend smaller Touchstone models with 10 aggressors. Scott said no, some of them take unacceptable shortcuts. A better approach is to extract the whole model, find the worst case, and only then possibly scale it back. Slide 5: This show the effect of going from 0 to 1 aggressor. Slides 6 to 8 show incrementally more aggressors. Scott this might be confused with Rj. Slide 9 shows the difference between 2 and 25 aggressors, 5.3ps. Slide 10 shows the difference between 5 and 25 aggressors, 2.4ps. Scott noted that is still a significant portion of a UI. Slide 11 concludes that a generalized modeling approach is recommended for future modeling. Model size can be an issue, but not a great one. Simulations can take 3 to 4 minutes. Crosstalk causes problems more readily than DFE issues. Walter agreed with Scott's points. Arpad asked if Scott had comments on recent emails about interconnect modeling. Scott has not been following closely, but in general he recommended simplifying. He said you only need to know where the drivers and receivers are. He also recommended a separate analysis of package only. Walter showed an EMD on-die presentation: On slide 8 Walter highlighted a statement that an s8p represents a full package minus power and ground. Arpad said Scott would call that a special case subset. Walter said it was a full model for the DQ bus, and asked if we want to support this. Scott said a bus with 8 bit byte lanes might be described in a generalized way, and that might allow full automation of analysis. Walter recommended this approach in lieu of BIRD 125. Scott noted that Output/Input information is sometimes wrong in IBIS files. Arpad said this was more common with FPGAs. Scott said FPGA tools are supposed to handle that correctly. ------------- IBIS Interconnect SPICE Wish List: 1) Simulator directives